| 摘要 |
PURPOSE: A circuit for generating a clock signal is provided to prevent a glitch without regard to a relay component while generating a clock signal. CONSTITUTION: A clock signal generation circuit includes a flip-flop(FF11), a flip-flop(FF12) and exclusive-OR gate(XOR11). The flip-flop(FF11) divides an input clock signal(CLK_IN) into two parts under the control of the clock enable signal(CLK_EN), and generates a center signal(TOG_Q). The flip-flop(FF12) performs a clocking about the center signal(TOG_Q) by using the input clock signal(CLK_IN), and generates another center signal(D_Q). The XOR11 performs an exclusive-OR operation about the center signals(TOG_Q),(D_Q), and generates a final clock signal(CLK_OUT). Thereby, the circuit prevents a glitch regardless of a relay component while generating a clock signal.
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