| 摘要 |
PURPOSE: A duty cycle correcting circuit is provided to be capable of promoting the information storage in a power saving mode and return to a normal mode by digitalizing information for correcting the phases of points in which duty cycles are matched to have a phase difference of 180 deg with a locking point. CONSTITUTION: A first clock delay adder(201) calculates continuous two clocks(CKn,CKn+1) to generate a clock(CLK) in accordance with a control signal(CTL). A second clock delay adder(202) calculates continuous two clocks(/CKn,/CKn+1) to generate a clock(/CLK) in accordance with a control signal(/CTL). A duty matching part(203) receives respective clocks(CLK,/CLK) of the first and second clock delay adders(201,202) to compensate their phases, thereby outputting clocks(DMC,/DMC) of 180 deg phase difference. An edge adder(204) receives the output signals(DMC,/DMC) of the duty matching part(203) to output a clock(DCLK) in a rising edge of the clock(DMC) as high and output a clock(DCLK) in a rising edge of the clock(/DMC) as low. First/second clock buffers(205,206) respectively output the output of the edge adder(204) to a main block and sub blocks.
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