发明名称 CHIP SIZE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
摘要 PURPOSE: A chip size package and a method for manufacturing the same are provided to increase a voltage level and reduce a noise by extending an area of a metal layer for grounding and power. CONSTITUTION: A chip size package and a method for manufacturing the same comprise a semiconductor chip, a first insulating layer(21), a metal pattern, a second insulating layer, and a solder ball. The semiconductor chip comprises a pad(11). The first insulating layer is formed on the semiconductor chip to expose the pad. The metal pattern is formed with a metal layer(40) connected with the pad for the power application. The second insulating layer is formed on an upper portion of the above structure to expose a ball land. The solder ball is mounted on an upper portion of the ball land.
申请公布号 KR20000066009(A) 申请公布日期 2000.11.15
申请号 KR19990012826 申请日期 1999.04.12
申请人 HYUNDAI ELECTRONICS IND. CO.,LTD 发明人 KIM, JAE MYEON
分类号 H01L23/13;(IPC1-7):H01L23/13 主分类号 H01L23/13
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