| 摘要 |
A memory device has an array of memory cells, including at least one memory block including multiple-level memory cells adapted for storing each one N>/=2 bits of information. The at least one memory block also includes electrically erasable and programmable bilevel memory cells, each for storing one bit of information. A circuit is provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals supplied to the memory device.
|
