| 摘要 |
An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them. The ALU is coupled to the alignment unit and receives and adds the aligned first and second inputs. The bypass datapath bypasses a predetermined one of the aligned inputs around the ALU. The bypass multiplexer is coupled with the ALU and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable a floating point to integer conversion if the other input is an integer conversion factor, and selects the ALU to enable an integer or floating point addition if the other input is an integer or floating point number.
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