| 摘要 |
An input data signal (10) is digitally sampled by a data sampling section (1) using an N-phase clock signal (11) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal (10) and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal (6) including N sample data signals is obtained. An edge point detection operation section (4) detects edge points in the N sample data signals in one cycle of an extracted clock signal (12) and outputs an edge point operation output signal (8). A clock signal extraction section (5) selects a clock signal from the N-phase clock signal (11) based on the information of the edge point operation output signal (8) and outputs the selected clock signal as the extracted clock signal (12). A delay section (2) delays the N sample data signals of the parallel sample data signal (6) and thereby outputs a parallel delayed sample data signal (7) including N delayed sample data signals. A data regeneration section (3) selects a delayed sample data signal from the N delayed sample data signals based on the information of the edge point operation output signal (8) and outputs the selected delayed sample data signal as a regenerated data signal (13). Due to the delay by the delay section (2), extraction time of the digital PLL circuit can be decreased to 0 without enlarging the overhead in the input data signal (10). <IMAGE> |
