| 摘要 |
PURPOSE:To optimize the relation of a phase of input data and a phase of an input clock by controlling the phase of the input clock so that both the phases have a set delay time relation. CONSTITUTION:An integration circuit 10b obtains a DC voltage output 19 with a level corresponding to a probability of a change in input data 13 and a delay time T given by a variable delay circuit 8. Moreover, a DC voltage output 18 corresponding to the probability of the change in data 13 and a phase delay phiD given to an input clock to a phase variable circuit 6 is obtained. The outputs 18, 19 are inputted to an operational amplifier 11 in which the output 19 is used for a reference signal, from which a control signal 20 corresponding to a phase difference phiD is inputted to the phase variable circuit 6. The circuit 6 uses its feedback loop to make the outputs 18, 19 equal to each other based on the control signal 20. That is, the phase of the input clock is controlled so as to obtain the relation of phiD=T and the resulting signal is outputted to an identification circuit 5. Thus, the phase difference phiD between the input data and the input clock inputted to the identification circuit 5 is kept equal to a delay time T of the delay circuit 8 automatically and made stable without external adjustment. |
