| 摘要 |
<p>An interlaced input image signal is supplied at a field frequency of 50 Hz. Class detection circuits detect classes corresponding to the patterns of the level distribution of input pixels near an output pixel to be produced. Prediction factor sets corresponding to the classes are read out of prediction factor memories. Product-sum operation circuits calculate data on the output image signals by using a linear estimation formula of estimation taps (pixels of the input image signals) and the prediction factor sets. The pixel values (M and S) of the output image signals of 50 Hz are outputted by the product-sum circuits. The pixel values (M and S) from the product-sum circuits are converted into signals of a frequency of 60 Hz. A selector selects one of the outputs of the field memories alternately and generates an output image signal (field frequency of 60 Hz).</p> |
