| 摘要 |
A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence control section (5) has two control registers (VL-MODE and VL-CNT). A CPU (2) sets the desired value to the control register (VL-MODE) to select a processing content to be performed by a VLC processor (4). A local memory (7) is realized by a 4K-byte RAM to store retrieval tables used in decoding or encoding process. The sequence control section (5) controls a second DCT buffer section (11), an address generating section (12), a DCT generating section (14), VLC generating section (14), a shifter section (15), a VLC buffer section (16), and a VLC pack section (17), so that the process indicated by the control register (VL-MODE) is executable.
|
