发明名称 ADDRESS CONVERSION CIRCUIT AND SEMICONDUCTOR MEMORY TESTING DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the load on a scramble memory, and to easily carry out multi-bit address conversion by the scramble memory with existing capacity by introducing a non-conversion address. SOLUTION: The address conversion circuit adds the lower bit of a logic address to a scramble memory 102 for converting into a physical address matching with the arrangement of a cell inside a memory to be measured. The converted physical address is given to the memory to be measured. The specific upper bit of logical addresses X, Y, and Z originally coinciding with the arrangement of the cell inside the memory to be measured is directly given to the memory to be measured as the physical address without any conversion, thus directly connecting the output of a logical address sector 101 to a physical address sector 103.
申请公布号 JP2000306396(A) 申请公布日期 2000.11.02
申请号 JP19990113670 申请日期 1999.04.21
申请人 ASIA ELECTRONICS INC 发明人 UMEZAWA MIZUKI
分类号 G06F12/16;G01R31/28;G01R31/3183;G06F12/02;G11C29/00;G11C29/10;(IPC1-7):G11C29/00;G01R31/318 主分类号 G06F12/16
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