发明名称 DEVICE AND METHOD FOR CONVERSION AND ENCODING
摘要 <p>PROBLEM TO BE SOLVED: To reduce the number of arithmetic circuits which are required at the time of detecting the motions of image signals in a rectangular block. SOLUTION: An FDCT circuit 11b outputs the DC factor of each line in a rectangular block as C0 and the DC factors are integrated by means of the sign selecting circuits 11d and 11g, adders 11e and 11h, and registers 11f and 11i of a motion detecting section after (+) or (-) sign is appropriately added to the DC factors. A comparator circuit 11j performs motion detection by comparing the absolute value of the integrated value outputted from the register 11f with that of the integrated value outputted from the register 11i.</p>
申请公布号 JP2000308057(A) 申请公布日期 2000.11.02
申请号 JP19990111921 申请日期 1999.04.20
申请人 VICTOR CO OF JAPAN LTD 发明人 HARUMATSU MITSUO;KINOSHITA KOSUKE
分类号 H04N19/12;H04N7/24;H04N19/00;H04N19/139;H04N19/14;H04N19/176;H04N19/186;H04N19/196;H04N19/51;H04N19/60;H04N19/625;(IPC1-7):H04N7/30 主分类号 H04N19/12
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