Semiconductor memory component with column selection circuit for selecting one of memory banks from memory block and for selecting specific bit line from selected bank, for use in e.g. Rambus DRAM

摘要

The column selection circuit contains a first selection region (122) for connecting the bit lines of the selected bank with 1st data lines depending upon a bank selection signal, a second selection region (124) for connecting the 1st data lines with second data lines depending upon a column selection signal, and a third selection region (126) for connecting the second data lines with the data input/out lines depending upon the bank selection signal. An Independent claim is also included for memory component set-up method.