| 摘要 |
<p>An apparatus to power up an integrated device from a low power state wherein the clock circuit for generating the internal clocks has been disabled is provided. A small set of programmable registers is reserved inside the CPU interface unit (CIF) of an integrated device (e.g., a display/graphics controller) which can be accessed by the CPU even during a low power state mode (e.g., software controlled sleep mode D3 in the preferred embodiment). The programmable registers store programmed bits that are used in indicating to the Power Management Unit (PMU) the desired power state and whether the clock circuits are to be enabled or disabled. The programmable registers also store multiplication and division factors to be used by the clock circuits in determining their clock rate. Using this information, the integrated device can go through a predetermined power sequence to transition from the low power state to the normal state which includes powering up the clock circuits (e.g., PLLs and oscillator).</p> |
