| 摘要 |
<p>PROBLEM TO BE SOLVED: To decrease skews of clocks of different phases while maintaining a delay by generating and arranging dummy blocks in exactly the same number and arrangement positions as the blocks which are connected to the clocks. SOLUTION: Cells are arranged (S1), and (n-1) pieces of dummy blocks are generated and arranged at a place near the FFs(flip-flops) to which the clocks (i) are connected (S2). Then, connecting relations are established between the dummy blocks and the clocks of different phases (S3). The clocks (i) are clustered (S5) and then clustered again in consideration of arrangement of FFs (S6). The buffers are generated and arranged at the positions where the load balance is secured for every cluster (S7). If the output destinations of buffers are all dummy blocks, these blocks and their connecting relations are deleted, and the arranged buffers are replaced with the dummy buffers (S8). This processing is repeated until i>=n is satisfied and the equivalent delay wiring is performed for a clock tree (S11).</p> |
