| 摘要 |
PURPOSE: An input circuit having a bias circuit owned jointly by a plurality of input buffers is provided to reduce the power consumption. CONSTITUTION: An input circuit having a bias circuit owned jointly by a plurality of input buffers includes a plurality of input buffers, here for example, 1 to 8(BUF1-BUF8). The bias circuit(110) including a bias signal generating section(101) and a current source section(121), generates a bias signal(VBIAS) having a regular voltage level. The bias signal generating section(101) is embodied as a primary NMOS transistor gates by the reference voltage(VREF). The primary NMOS transistor has a source terminal which is grounded, and a drain terminal connected to an output terminal of the bias circuit(110). The bias signal(VBIAS) provide the primary NMOS transistor with a drain voltage. The current source section(121) is embodied as a primary PMOS transistor gated by the bias signal(VBIA). The primary PMOS transistor includes a source terminal connected to an inner power supply voltage(VCC) and a drain terminal connected to a gate terminal and the train terminal of the primary NMOS transistor in common. Each of the 1 to 8 input buffers(BUF1-BUF8) includes 1 to 8 signal generating sections(111-118) and 1 to 8 current mirror sections(131-138), and receives the bias signal(VBIAS) of the bias circuit(110) in common. And corresponding data signals(DATA1-DATA8) in CMOS level, are generated by comparing the level of the reference signal(VREF) with input signals(VIN1-VIN8).
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