SINGLE POLY EEPROM CELL LAYOUT AND MANUFACTURING METHOD THEREOF

摘要

PURPOSE: An EEPROM cell layout and method for fabricating an EEPROM cell are to prevent a bottleneck of a poly when a cell size is decreased. CONSTITUTION: A method for manufacturing an EEPROM cell having a select transistor connected to a word line(102b) and a sense transistor connected to a sense line(100b) comprises the steps of: defining an active region(100a) and an inactive region(104) of a semiconductor substrate; forming a first insulating film on the semiconductor substrate; etching the first insulating film on the inactive region; ion implanting to form a first conductive region on the active region; etching the first insulating film by using a tunnel region(101) forming mask; forming an oxide film at the tunnel region with the first insulating film etched therefrom; forming a conductive film on the whole surface of the semiconductor substrate; etching the conductive film by using the word line and the sense line forming mask; forming a high pressure junction region on the active region; and ion implanting to form second and third conductive regions at the high pressure junction region.