发明名称 |
MULTIPLIER HAVING LOW POWER CONSUMPTION |
摘要 |
PURPOSE: A multiplier having a low power consumption is provided to minimize a power consumption by using a modified bus algorithm. CONSTITUTION: A multiplier part output unit(100) multiplies an input signal in accordance with a modified bus algorithm. A carry non-delivery adder(110) adds an output signal of the multiplier part output unit(100) to another input signal without transmitting a carry. The carry non-delivery adder(110) is constructed as a CSA tree. An adder(120) adds an output signal received from the carry non-delivery adder(110) and generates a final output. The multiplier having a low power consumption is formed by the type of a PPG, a CSA and a CPA.
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申请公布号 |
KR20000061677(A) |
申请公布日期 |
2000.10.25 |
申请号 |
KR19990010896 |
申请日期 |
1999.03.30 |
申请人 |
HYUNDAI ELECTRONICS IND. CO.,LTD |
发明人 |
KIM, GYEONG TAE;LEE, JAE YONG |
分类号 |
G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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主权项 |
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地址 |
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