Logic circuit delay stage and delay line utilizing same

摘要

The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.