发明名称 CACHE MEMORY DEVICE AND CACHE MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To implement substitute algorithm by a programmer by selecting a cache set or its group when a specific value is stored in the specific bit area of an entry of a high-speed converting buffer mechanism. SOLUTION: The high-speed converting buffer mechanism (TLB) 41 of a memory management (MMU) 4 has multiple entries, which is each stored with a virtual page address VPN, a physical page address PFN, an effective bit V, and extension C bits so that they correspond to one another. The extension C bits are information obtained by adding information specifying a cache set to information of the C bits indicating a conventional cache coherency property. Then a selector 5 selects one of 0th and 1st cache sets 31 and 32 according to the value of the extension C bits included in data outputted from the MMU 4. Further, a controller 6 makes one of the 0th and 1st cache sets 31 and 32 active when the extension C bits are '11'.
申请公布号 JP2000293437(A) 申请公布日期 2000.10.20
申请号 JP19990096858 申请日期 1999.04.02
申请人 NEC CORP 发明人 NAKAMURA YOSUKE
分类号 G06F12/08;G06F12/10;(IPC1-7):G06F12/08 主分类号 G06F12/08
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