发明名称 Bohrkoordinaten-Optimierung für mehrschichtige Leiterplatten
摘要 A multilayer printed circuit board (40) consists of dielectric layers (40A, 40B, 40C, 40D) . Prior to lamination, each corner of each layer is marked with a test pattern consisting of two conductor lines (32A, 32B, 32C, 32D) and (34A, 34B, 34C, 34D) which intersect to form a cross. The test patterns are located in the same nominal positions so that, under ideal conditions, the test patterns of the layers in each corner are lined up one above the other, without any offset. A counter sinking tool (45) is used to cut a conical bore (42) in the location of the test patterns, so that every test pattern cross is interrupted in four places, generating a four segment pattern in each layer. The patterns of different layers create concentric circles in the bore. A high resolution camera is placed above the countersunk bore to form a single image of the exposed segment edges of all the test patterns exposed by the bore. The image is analyzed to determine the amount of shift of each layer. If all patterns are perfectly concentric, all crosses are perfectly aligned. By measuring the shift of each pattern from the nominal position, the amount of shift in each layer is determined. The process is repeated for the test patterns at each corner of the board, and the resultant layer shift data is processed to optimize the drilling pattern for the board. <IMAGE>
申请公布号 DE69514016(T2) 申请公布日期 2000.10.19
申请号 DE1995614016T 申请日期 1995.02.28
申请人 DYNAMOTION/ABI CORP., SANTA ANA 发明人 KOSMOWSKI, WOJCIECH B.;RUDOLPH, JOHN M.
分类号 B23Q17/22;B23Q17/24;H05K1/02;H05K3/00;H05K3/46;(IPC1-7):H05K3/00;G01R31/28 主分类号 B23Q17/22
代理机构 代理人
主权项
地址