| 摘要 |
<p>A power amplifier is proposed for applications having a low single-ended supply voltage and a high required output power. The amplifier includes a FET (10) with its gate coupled to an input (Pin) and its drain coupled to an output (pin) via an impedance matching stage (60, 70). The transistor gate is biased by an impedance (30) and a source biasing element (90, 91) shunted by a bypass capacitor (80, 81) couples the source to ground. A common terminal (A) is provided between the transistor source and the impedance matching stage, and is connected to ground through the source biasing element. This has the effect of raising the impedance at the source perceived by the bypass capacitor. The peak currents passing through the source bypass capacitor element can thus be considerably reduced, specifically to a level which allows the capacitor to be of a more manageable size, and to be implemented on chip.</p> |
