发明名称 |
Sensing circuit for a memory cell array |
摘要 |
The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.
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申请公布号 |
US6134164(A) |
申请公布日期 |
2000.10.17 |
申请号 |
US19990296876 |
申请日期 |
1999.04.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP. |
发明人 |
LATTIMORE, GEORGE MCNEIL;YEUNG, GUS WAI-YAN |
分类号 |
G11C7/06;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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