发明名称 Method of manufacturing semiconductor device having multilayer interconnection structure
摘要 A method of manufacturing a semiconductor device copes with miniaturization owing to reduction in an overlapping margin. According to this manufacturing method, a conductive layer forming an upper interconnection layer is formed in an opening provided for connection to a lower interconnection layer, and then an organic polymer film filling a concavity at the conductive layer located in the opening is formed. After forming a resist pattern on the organic polymer film, organic polymer film and conductive layer are etched. The overlapping margin is reduced owing to the fact the organic polymer film fills the concavity at the conductive layer.
申请公布号 US6133138(A) 申请公布日期 2000.10.17
申请号 US19980009177 申请日期 1998.01.20
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 ISHIBASHI, TAKEO
分类号 H01L21/768;H01L23/522;(IPC1-7):H01L21/476 主分类号 H01L21/768
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