| 摘要 |
A NOR array architecture allowing single bit, row, and column programming and erase operations is disclosed. The NOR array architecture comprises: a plurality of ETOX cells formed in a deep n-well, each of the ETOX cell having: (1) a control gate; (2) a floating gate insulated from and formed substantially underneath the control gate; (3) a p-well formed in the n-well and underneath the floating gate and the control gate; (4) a drain implant formed in the p-well adjacent to the floating gate; and (5) a source implant formed in the p-well adjacent to the floating gate. The ETOX cells are formed into a two-dimensional array including a plurality of rows and a plurality of columns. Each of the control gates of the ETOX cells in adjacent two rows sharing a common row are connected to a row wordline. Each of the source implants of the ETOX cells sharing a common row are connected to a row sourceline. Each of the drain implants of the ETOX cells sharing a common column are connected to a column bitline. Finally, each of the p-wells of the ETOX cells in a common column are connected together to a common p-well bias line.
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