REFRESH CIRCUIT OF SYNCHRONOUS DRAM

摘要

PURPOSE: A refresh circuit of a Synchronous DRAM(SDRAM) is provided which includes a function to refresh a word line needed to be refreshed selectively without adding an additional pin in a conventional standard SDRAM. CONSTITUTION: A refresh circuit of a SDRAM improves the performance of the whole system, and can reduce the refresh cycle by performing refresh by selecting a word line required to be refreshed. The refresh circuit includes: a control signal input buffer(21) outputting signals by synchronizing an input signal inputted from the external and a column operation control signal(DQM) to a clock signal; a command generating part(22) which generates a first or a second refresh command by receiving a logic assembly signal of an output signal applied from the control signal input buffer according to the column operation control signal; a row activation part(23) generating a control signal to activate the row operation according to the first or the second refresh command; a row activation control part(24) to control the row activation part; an internal address counter(25) generating a random internal address signal according to the first refresh signal; an external address path to input an address of the corresponding word line to refresh; a row predecoder(26) receiving the internal address applied from the internal address counter or the external address applied through the external address path according to the control signal applied from the row activation part and decoding them as a row address signal of a fixed bits; a word line model signal generating part(27) generating a word line model signal when an actual word line is selected according to the first or the second refresh command; and a sense amp state predicting part(28) outputting a signal indicating the amount sensing of a sense amp to the row activation control part.