| 摘要 |
PURPOSE: A semiconductor memory device having shared data line contacts is provided to provide a lay-out of a transistor for column selection line appropriate for large integration. CONSTITUTION: An active region(1) for transistors selecting bit lines(BL0,BL1) to be connected to corresponding data lines(IO0,IO0B) is arranged on both edges in order for a source/drain contact to be shared by adjacent selection transistors. According to the layout, it is possible for the selection transistors to be layed out within a pitch of (L+S+2alpha). Two pairs of data lines(IO0,IO0B,IO1,IO1B), that is, four data lines are provided in a DRAM device. The above two pairs of data lines are shared by another adjacent memory cell array.
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