| 摘要 |
<p>PROBLEM TO BE SOLVED: To enhance the general-purpose performance of a device for converting ATM cell format where even an LSI by CMOS or Bi-CMOS process can process ATM cells of a high speed data stream and a bus width in 32-bit well compatible with a CPU can be adopted. SOLUTION: Upon the receipt of a transmission cell and a cell head identification signal SOC from an ATM layer device, a write timing control 2 does not write idle bytes of a received cell to a memory 7 when a format of the received cell indicates bytes larger than 53 bytes and reserves deficient bytes in the memory 7 when less than 53 bytes. The transmission cells are written in memory areas designated by the write timing control 2 via a 1st rotator 1 without any idle area. The memory 7 consists of areas whose number is the same as number of bytes of the transmission cells received from an ATM layer. When the write is finished, reading is started by a phase control signal PCONT. A read timing control 4 reads cells from the memory 7 and outputs them via a 2nd rotator 6.</p> |
