Memory cell structure, especially for a DRAM, has a contact within a substrate for connecting a capacitor and a MOS transistor on opposite substrate surfaces

摘要

A memory cell structure comprises a contact (K) within a substrate (S) for connecting a capacitor and a MOS transistor on opposite substrate surfaces (O1, O2). A memory cell structure comprises a MOS transistor connected to a bit line (B) on one substrate surface (O1), a capacitor on the opposite substrate surface (O2) and a contact (K) in the substrate (S) for connecting the capacitor with the MOS transistor. An Independent claim is also included for production of the above memory cell structure.