TEST SCAN CIRCUIT OF INTEGRATED CIRCUIT

摘要

PURPOSE: A test scan circuit of an integrated circuit is provided to form a scan input terminal receiving scan patterns regardless of the number of scan chains. CONSTITUTION: A test scan circuit of an integrated circuit includes the followings. A test enable terminal(test_enable) receives test mode setting signal. A scan data generating section(110) receives scan patterns through scan input terminal(scan-in) generates N number of scan patterns(scan pattern 1-scan pattern N). Scan chain 1 to scan chain N receive test enable terminal(test_enable) and the N number of scan patterns(scan pattern 1-scan pattern n) and outputs through N number of scan output terminals(scan-out 1 - scan-out N). The scan data generating section(110) has a scan input terminal receiving scan patterns regardless of the number of scan chains with N-1 number of flip flops and N-bit register.