发明名称 Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs
摘要 An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.
申请公布号 US6128171(A) 申请公布日期 2000.10.03
申请号 US19990236100 申请日期 1999.01.25
申请人 PMC-SIERRA LTD. 发明人 INIEWSKI, KRIS;SYRZYCKI, MAREK
分类号 H01L23/60;H02H9/00;(IPC1-7):H02H9/00 主分类号 H01L23/60
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