| 摘要 |
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes plural columns of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each logic function unit (VGB) is organized to process a nibble of data. Each embedded memory block is multi-ported and organized to store addressable nibbles of data. Interconnect resources are provided for efficiently transferring nibbles of data between the logic function units (VGB's) and corresponding memory blocks. Further interconnect resources (SVIC's) are provided for supplying address and control signals to each memory block. In one embodiment each memory block has at least one read-only port and at least one read/write port that are individually addressable and individually switchable into high output impedance tri-state modes.
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