COLUMN BUFFER CIRCUIT OF HIGH SPEED MEMORY

摘要

PURPOSE: A column buffer circuit for a high speed memory is provided to reduce a column access time by implementing a column access operation based on a combination of a column cycle signal and a column latch signal in a read mode. CONSTITUTION: An inverter(INV1) inverts a column cycle signal(COLCYC). A NOR gate(NR1) NORs a delay column latch signal(COLLAT) delayed by a delay unit(dly) for a certain time with a column cycle signal(COLCYC). An inverter(INV2) inverts a write signal(WRITE). Transmission gates(G1 and G2) are alternately turned on in response to an output signal of the inverter(INV2). An inverter(INV3) inverts an output signal of the transmission gate(G1) in a write mode and inverts an output signal of the transmission gate(G2) in a read mode and outputs a CAS signal. A NOR gate(NR2) NORs an output signal of the transmission gate(G2) and a bank signal(clbanki) and outputs a CASFi signal. The read mode and write mode are recognized by a write signal(WRITE). If the write signal is high, it means a write mode, and if the write signal is low, it means a read mode.