发明名称 LOGICAL SIMULATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To reduce the number of evaluating times by executing the evaluating arithmetic processing of a flip-flop regarding it as a flip-flop element which should by evaluated to be a time when the operating condition of the flip-flop element to be an evaluating object is coincident with event information of its synchronizing signal. SOLUTION: When a flip-flop element to be an evaluating object exists in a time, processing equal to or less than the preparing number of an execution process list 102 is executed and it is judged whether an event is generated with respect to a synchronizing signal for controlling the flip-flop element by referring to synchronizing signal variation information of the list 2. When the event is generated in the synchronizing signal by this decision, the variation information is obtained from a signal information table 101. Then, when the variation information of the synchronizing signal is coincident with the operating condition of the flip-flop element, the flip-flop element is regarded as one which should be evaluated to be a time by referring to evaluating arithmetic information 104 and evaluating arithmetic processing of the element is executed.
申请公布号 JP2000268059(A) 申请公布日期 2000.09.29
申请号 JP19990067827 申请日期 1999.03.15
申请人 HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD 发明人 NAKAI TOMOAKI;TOMITA HIROSHI;FUKASE YOSHIHIRO;HOSAKA TERUO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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