Semiconductor memory device with high data read rate

摘要

A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.