| 摘要 |
PROBLEM TO BE SOLVED: To provide a high digital signal processor performance with a little power consumption by decoding a software breakpoint instruction having a length equal to any one of instruction length formats. SOLUTION: An instruction buffer unit 106 decodes an instruction, which is fetched from an instruction memory, having a first length selected out of plural first instruction fetch lengths. The decoded instruction is executed by a data calculation unit 112 and a program counter generates an instruction address to be provided to the instruction memory. Namely, the instruction buffer unit 106 operates to decode the first software breakpoint instruction selected to have a length equal to any one of plural first instruction length formats. Besides, the instruction buffer unit 106 operates to decode the second software breakpoint instruction coupled with a first non-operation instruction in one cycle.
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