发明名称 |
DUPLICATE SYSTEM AND SIGNAL SYNCHRONIZATION CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a duplication system that is operated independently of a scale of a clock skew between dual systems in a duplicate system that is operated by a clock step synchronously with a clock signal. SOLUTION: A flip-flop 30 fetches an input signal A at a leading edge of a clock A in this duplicate system. A flip-flop 31 fetches an output of the flip- flop 30 at a leading edge of a clock B and a flip-flop 33 fetches the output at a trailing edge of the clock B. A selector 41 selects an output of the flip-flop 32 in the case of an operating mode 0 or selects an output of the flip-flop 31 in the case of an operating mode 1 according to the mode depending on a magnitude of skew of the clocks A, B. A flip-flop 33 fetches the signal selected by the selector 41 at a leading edge of the clock B and provides an output of an output signal (A-B). |
申请公布号 |
JP2000261419(A) |
申请公布日期 |
2000.09.22 |
申请号 |
JP19990061366 |
申请日期 |
1999.03.09 |
申请人 |
HITACHI LTD |
发明人 |
MIYAZAKI NAOTO;YAMAGUCHI SHINICHIRO;TAKEHARA TAKESHI;FUJIWARA MICHIO |
分类号 |
G06F13/42;G06F1/04;H03L7/00;H03L7/24;H04L1/22;H04L7/00 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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