发明名称 |
Semiconductor memory device capable of performing test mode operation and method of operating such semiconductor device |
摘要 |
Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external +E,ovs RAS+EE signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.
|
申请公布号 |
USRE36875(E) |
申请公布日期 |
2000.09.19 |
申请号 |
US19950572516 |
申请日期 |
1995.12.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
IWAMOTO, HISASHI;KUMANOYA, MASAKI;DOSAKA, KATSUMI;KONISHI, YASUHIRO;YAMAZAKI, AKIRA |
分类号 |
G01R31/28;G11C7/00;G11C11/401;G11C11/406;G11C29/00;G11C29/14;G11C29/46;H01L21/66;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|