| 摘要 |
PROBLEM TO BE SOLVED: To provide an event type test system reducing size of memory by compressing and storing event data for generating an event to be used for a test of a tested semiconductor device (DUT). SOLUTION: This event type test system is constructed of a clock count memory 20 storing clock count data comprising one or more data words in compliance with an integral part data, a vernier data memory 21 storing two or more vernier data in the same memory position, an address sequencer 18 generating address data for accessing the clock count memory 20 and the vernier data memory 21, and a decompressor 22 reproducing the clock count data from the clock count memory 20 and reproducing the vernier data from the vernier data memory in compliance with respective events.
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