| 摘要 |
PROBLEM TO BE SOLVED: To optimize a required clock by providing respectively program input coupled to an output of a selecting circuit giving a selecting signal indicating delay in plural programmable delay circuits. SOLUTION: At the time of normal operation, the output that is a common clock signal is given responding to a block selection signal delay to a delay adjusting circuit 80 that is decided by a fuse circuit 24. The delay adjusting circuit 80 performs programmable delay responding to a selecting signal given by a fuse circuit 24. The fuse circuit 24 adjusts delay of the delay adjusting circuit by giving binary bit data. Fuse circuits 24, 34 are cut off in accordance with electrical measurement obtained after the processing performed under a state where an integrated circuit 10 is electrically tested. An electrical test is used for deciding the delay being optimum for a delay adjusting circuit 32. Thus, a shortest delay where data can be detected reliably from each memory cell is decided. |
