| 摘要 |
A graphics subsystem having a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), which has a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The graphics subsystem may be formed on a single semiconductor chip. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address. |
