CENTRAL PROCESSOR AND METHOD FOR REDUCING POWER CONSUMPTION OF ITS CENTRAL PROCESSOR

摘要

PROBLEM TO BE SOLVED: To obtain a central processor which can be reduced in power consumption by stopping an unnecessary current from flowing in and out of a CPU while a controlled system is in a standby state and the power consumption reducing method for the central processor. SOLUTION: The central processor 104 are equipped with a power source control signal terminal 106, a 1st control signal terminal 107, and a 2nd control signal terminal 108 which are pulled up to a source voltage through resistors R1 to R3 and connected to a power source 112, a 1st controlled system 113, and a 2nd controlled system 114 respectively. This central processor 104 is equipped with a flag switching means 111 which places in the control signal terminals 106 to 108 in a high-impedance state when the power source 112, 1st controlled system 113, and 2nd controlled system 114 enter a standby state.