| 摘要 |
A clock circuit which selectively outputs a clock signal of a frequency equal to an integer multiple of a frequency of a master clock signal includes a setting circuit which sets a value corresponding to a target frequency of the clock signal, a counting circuit which counts pulses of the master clock signal, and an extracting circuit which extracts a pulse of the master clock signal each time a counter value of the counting circuit becomes equal to the value set by the setting circuit.
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