SYNCHRONIZED DATA FETCH CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a synchronous data fetch circuit that synchronously captures data at a frequency substantially higher than a frequency of each data line and can use a step-down voltage signal. SOLUTION: The synchronous data fetch circuit 200 is provided with a timer generator 206 provided with a 1st timer generator output side, a 1st data driver circuit 210 consisting of a plurality of data drivers that receives a plurality of 1st data signals and a plurality of timing signals, and a 1st data clock circuit 214 that receives a data stream with a 1st high frequency and a 1st high frequency timing pulse stream. Thus, fetch of data in the 1st high frequency data stream is synchronized by using the 1st high frequency timing pulse stream and a synchronized data capture signal is outputted.