发明名称 |
Central processing unit with reduced power consumption |
摘要 |
<p>The invention relates to a clock controller circuit for performing a power saving feature in high performance microprocessors. The invention utilizes two logic gates and a flip flop for disabling a clock signal to an execution unit or ALU when data is not available for the execution unit or ALU. The invention provides a sleep mode or clock idle mode for an execution unit when data is not available for the execution unit because memory units, I/O devices, or internal caches are unable to provide data or instructions to the execution unit. The clock controller circuit disables the clock signals by gating the clock signal to a logic high. The clock controller circuit stops the clock signals in response to a no data available signal from a bus unit and a data required signal from the execution unit. &lt;IMAGE&gt;</p> |
申请公布号 |
EP0579369(B1) |
申请公布日期 |
2000.09.06 |
申请号 |
EP19930304316 |
申请日期 |
1993.06.03 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
MACDONALD, JAMES R. |
分类号 |
G06F1/04;G06F1/32;G06F9/38;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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