发明名称 Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel
摘要 In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.
申请公布号 US6115806(A) 申请公布日期 2000.09.05
申请号 US19980056650 申请日期 1998.04.08
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 YOSHIDA, TOYOHIKO
分类号 G06F9/30;G06F9/32;G06F9/38;(IPC1-7):G06F3/30 主分类号 G06F9/30
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