| 摘要 |
PURPOSE: A state machine of a universal asynchronous transceiver(UART) preventing a glitch of received serial data is provided to prevent the glitch, and to exactly recognize a received data value by detecting an idle state, a preliminary starting state, a starting state, a transmitting state, a parity state and a stock state, and to exactly recognize a received data value. CONSTITUTION: A state machine of a universal asynchronous receiver and transmitter(UART) preventing a glitch of received serial data comprises an idle state detecting circuit(1000), a first clock generator(2600), a preliminary starting state detecting circuit(200), a second clock generator(3600) and a starting state detecting circuit(300). The idle state detecting circuit(1000) generates a first outputting signal by responding to a logic signal transmitted from a logic which decides whether data is received, and a clock signal of a receiver. The preliminary starting state detecting circuit(200) generates a second outputting signal notifying a preliminary starting state by responding to a first clock signal and a first outputting signal. The second clock generator(3600) generates a second clock signal. The preliminary starting state detecting circuit(200) includes a signal transmitter by performing a logic AND of the second outputting signal, a receiving available signal applied from an external and a reversed serial receiving signal. The preliminary starting state detecting circuit(200) generates a third outputting signal notifying a data receiving state by responding to the second clock signal and an outputting signal of the signal transmitter. The first clock generator(2600) comprises a first inverter(210), a second inverter(220) and an AND gate(250). The first inverter(210) reverses the serial receiving signal. The second inverter(220) reverses the second outputting signal. The AND gate(250) generates a first clock by receiving the reversed signals. The first clock resets the idle state circuit by the serial receiving signal. If the second outputting signal is generated, an input reset by the glitch is not transmitted to the preliminary starting detecting circuit.
|
