| 摘要 |
PURPOSE: A circuit for resetting a power on is provided to reduce a chip size without a resistor and a capacity, by using inverters and buffers delaying outputs of the inverters to generate a resetting signal. CONSTITUTION: A circuit for resetting a power on comprises inverters(1NV1-INV3), an inverter(INV4), a first buffer and a second buffer(BUF1,BUF2), an inverter(INV5), a third buffer(BUF3), an AND gate and a D flip-flop. The INV1-INV3 reverse a receiving crystal signal as each different inverting voltage, and output the reversed crystal signal. The INV4 reverses an output of the INV1. The BUF1 and BUF2 delay an output of the INV4 during a predetermined time. The INV5 reverses an output of the INV2. The BUF3 delays an output of the INV5 during the predetermined time. The AND gate perform a a logical AND the outputs of the BUF2 and the BUF3 and an output of the INV3. The D flip-flop receives an output of the AND gate to a data inputting terminal(D) through a 4 buffer(BUF4), and receives the output of the INV5 as a clock(CK). The circuit checks whether a full swing of the crystal is performed by passing the INV1-INV3 having an inverting transposition of 4 voltage, 2.5 voltage, and 1 voltage by receiving the crystal signal with an insecure state. The circuit checks whether a rising gradient and a falling gradient of the crystal signal are as fast as being included within a delayed time of a pre-used buffer by using a delaying buffer and the AND gate. The circuit checks whether the crystal signal is at a normal state by through the insecure state, and makes a signal resetting the power on by using a generated signal.
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