发明名称 |
A SYMMETRIC FILTERING BASED VLSI ARCHITECTURE FOR IMAGE COMPRESSION |
摘要 |
An apparatus to perform symmetric filtering image compression is provided. The apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image. The apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs. The apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs. Additionally, the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits. The apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits. |
申请公布号 |
WO0051356(A1) |
申请公布日期 |
2000.08.31 |
申请号 |
WO2000US01963 |
申请日期 |
2000.01.25 |
申请人 |
INTEL CORPORATION;PAZMINO, EDWARD, A.;ACHARYA, TINKU;VAVRO, DAVID, K. |
发明人 |
PAZMINO, EDWARD, A.;ACHARYA, TINKU;VAVRO, DAVID, K. |
分类号 |
G06T5/20;G06T9/00;H04N1/41;H04N7/26;H04N7/30;(IPC1-7):H04N7/26;G06F17/14 |
主分类号 |
G06T5/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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