Post-synchronisation method for clock signals, with continuous clock-signal/reference-signal comparison

摘要

A clock signal post sync method involves the steps of initially dividing a first clock signal (f1) up into a second clock signal frequency (f2) by using a programmable digital frequency divider (2). The second clock signal (f2) is then measured by a digital control circuit (8,6,4) and the programmable digital frequency divider is then programmed by the digital control circuit (4) so that the second clock signal (f2) corresponds to a specifiable clock signal (fout). The digital control circuit (4) measures the second clock signal (f2) in time intervals specified by the third signal (f3).