发明名称 Nonvolatile semiconductor memory device capable of decreasing layout area for writing defective address
摘要 A latch circuit functions as a write latch circuit when writing a defective address into a nonvolatile semiconductor memory cell array. The latch circuit also functions as a defective address latch circuit when the power voltage rises. Therefore, the layout area of the defective address setting circuit can be reduced as compared with the defective address setting circuit of the conventional flash memory of the FN-FN type provided with a write latch circuit and a defective address latch circuit.
申请公布号 US6111785(A) 申请公布日期 2000.08.29
申请号 US19990379009 申请日期 1999.08.23
申请人 SHARP KABUSHIKI KAISHA 发明人 HIRANO, YASUAKI
分类号 G11C16/06;G11C8/06;G11C16/08;G11C29/04;(IPC1-7):G11C16/06 主分类号 G11C16/06
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